The invention is generally related to the field of semiconductor device fabrication and more specifically to a method for reducing channeling and latchup in shallow trench isolation structures by implanting through nitride.
In current VLSI technology for fabricating submicron CMOS integrated circuits, high energy ion implantation is used for making retrograde wells. In retrograde wells the carrier concentration deep in the silicon substrate is greater than the carrier concentration at the surface. In general, retrograde wells are useful for the following reasons: their ability to put high concentration of dopants at specific desired locations, their low thermal budget (no high thermal budget well formation required), their reduced cost and processing complexity by having all the channel implants done at the same mask level, and their improvement in soft-error immunity. The high energy (MeV) implants require some changes in the processing steps compared to the non-MeV implant processing. The MeV implant requires photoresist that is a couple of microns thick to prevent the ions from penetrating it in the masked-off regions. For such thick photoresist, the channel implants need to be done at zero degrees. At any other angle, the implant will shadowed in the device region which could lead to a reduction in device performance and/or device failure. Shadowing also causes the well implant to be shifted laterally from its zero degree implant position. Implants done at zero degrees in (100) silicon result in channeling. At other angles, the implants will be dechanneled depending on the tilt angle of the implant. The dechanneled dopant profiles differ from the channeled implants in the tail region of the profile. In case of a boron channeled implant, there is a prominent second peak; for a completely dechanneled boron implant, the peak is small or absent. In the case of phosphorus channeled implant, there is a long tail; for a completely dechanneled phosphorus implant, the tail is very small or absent. Since the total implanted dose is the same in all implants, the nonchanneled implants will have higher peak concentrations compared to the channeled implants. Thus, the net effect of increasing the implant tilt angle is to cause the well doping profiles to be shifted laterally, decrease the dopant channeling tail, and increase dopant peak concentration.
Given the current feature sizes of shallow trench isolation (STI) structures, it is necessary to use zero degree high energy implants to form the retrograde well structures. For zero degree high energy implants, the center of the silicon wafer or substrate has channeling implants, and the left and right edges have nonchanneling implants. This causes a variation in the punch through voltage, leakage current, and latchup characteristics of transistors fabricated in these substrates. In general, this variation in transistor characteristics occurs in both 6-in and 8-in wafers with the effect being more pronounced in the larger wafers.
As the feature size of the transistors decrease, the spacing between transistors will also decrease. This reduction in spacing is accomplished by reducing the feature size of the STI structures. As the STI feature size is reduced, the effect on the transistor characteristics of channeling during retrograde well formation will become more pronounced. This channeling could eventually lead to complete failure of the integrated circuit. There is therefore a great need for a method of formation of retrograde wells with reduced dopant channeling.
The instant invention is a method of forming retrograde wells in silicon integrated circuit fabrication with reduced channeling effects. The method comprises forming silicon nitride films on the surface of the wafer after the formation of the isolation structures. By performing the retrograde well implants through these silicon nitride layers, channeling is reduced.